The invention relates to fabrication of a complementary bipolar transistor pair and, in particular, to a shallow profile vertical PNP transistor integrated with a shallow profile vertical NPN transistor wherein the gain of the pnp device is at least 10-15 (at 1 ma) and cutoff frequency is at least 1-4 GHz.
The fundamental advantage of a complementary bipolar device is its low power consumption, i.e., the amount of current that the device consumes in accomplishing the push-pull function in some driver circuit or some logic function will be extremely low compared to a noncomplementary transistor arrangement. As technology evolves toward higher chip densities and power consumption by the chip is severely limited, ways must be found to obtain the same performance with a reduced power consumption.
Many efforts have been directed at producing complementary PNP and NPN transistor pairs on a common monolithic semiconductor substrate. Generally, two problems have been encountered in producing complementary transistor pairs. First, because of the lesser mobility of holes relative to electrons, PNP transistor characteristics are inherently inferior to those of NPN transistors. PNP transistors usually have a current gain of no higher than about 10 and a cutoff frequency of no higher than about 500 MHz, whereas NPN transistors generally have a gain in excess of about 80 and cutoff frequency in excess of about 3.5 GHz. Consequently, PNP transistors, particularly the lateral PNP transistors which are inferior to vertical PNP devices, are generally used as load devices and their characteristics are not relied on as a means of determining logic speed of a logic circuit or switching speed of driver
U.S. Pat. No. 3,730,786 to Ghosh and assigned to the present assignee, describes a method for fabricating a complementary pair of bipolar transistors. A significant feature of the Ghosh patent is the use of a highly doped N+ region formed at the surface of the substrate to act as a barrier for the PNP transistor device. In subsequent steps of the method of the Ghosh patent, the N+ doped region diffuses into the subsequently deposited epitaxial layer. Through ion migration and autodoping, a highly doped barrier region is formed which is superimposed over the subcollector region of the PNP transistor. The intersection of the N+ doped barrier region with the P subcollector of the PNP transistor forms a PN junction which may act to provide NPN transistor function during operation of the structure. The Ghosh patent relies upon boron diffusion to form the emitter region of the PNP emitter, but the PNP emitter contact is not self-aligned to the PNP emitter.
U.S. Pat. No. 4,485,552 to Magdo et al an assigned to the present assignee describes a method of making complementary vertical NPN and PNP transistors in which the PNP collector is formed by double diffusion of dopant into a substrate. Then, an N-type epitaxial silicon layer is formed by deposition on the substrate surface. The PNP emitter is formed by means of a P+ doped polysilicon as a dopant diffusion source. Although this process provides a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer, it suffers from poor base width control of the PNP device due to its dependence on epitaxial layer thickness control and P+ outdiffusion.
U.S. Pat. No. 4,412,376 to DeBar et al and assigned to the present assignee, describes a vertical PNP transistor in which the emitter is a Shottky diode contact. A structure of this type, in general, tends to have inferior device characteristics compared to a PNP transistor having a P+ doped emitter.
U.S. Pat. No. 3,930,909 to Schmitz et al, like the Magdo et al patent, features pre-epi doping of the PNP collector with differential out-diffusion in the fabrication of complementary vertical transistor pair. The emitter of the PNP device is provided with the same doping profile as the base of the NPN device resulting in poor PNP device characteristics. Additionally, the PNP emitter is not self-aligned to the PNP emitter contact.
U.S. Pat. No. 3,885,999 issued to Fusaroli et al describes a method of forming a lateral PNP transistor in conjunction with a vertical NPN transistor. The lateral PNP structure basically suffers from poor device characteristics and low gain at normal emitter current densities. A lateral PNP structure while useful as a load device in bipolar array designs, suffers from insufficient frequency response forr complementary logic applications.
U.S. Pat. No. 3,617,827 issued to Schmitz et al, like U.S. Pat. No. 3,930,909 relies on differential outdiffusion to form the P collector of a complementary vertical PNP and NPN transistor pair. The P collector is not isolated from the P substrate; the PNP emitter is not self-aligned to the PNP emitter contact; and the PNP device is required to be deeper than the NPN device. Cumulatively, these requirements result in a PNP transistor having a frequency response much inferior to that of the NPN transistor.
The German Offenlegungschrift No. 24 28 881 shows a complementary bipolar transistor pair consisting of a lateral PNP transistor and a vertical NPN device.
U.S. Pat. No. 4,339,767 to Horng et al an assigned to the present assignee addresses lateral PNP transistor integrated with a vertical NPN device. The PNP emitter and collector impurity concentration profiles are defined by out-diffusion from P+ polysilicon dopant diffusion source and the base width is lithographically defined.
IBM Technical Disclosure Bulletin entitled "Complementary Transistors" by Jacobus et al, Vol. 14, No. 4, Page 1045, September 1971 describes a double N type epitaxial silicon deposition method for forming a vertical PNP transistor. The second epitaxial layer serves as both the base of the PNP and collector of the NPN. Base doping of this structure requires a wide (at least 1 .mu.m width) PNP base relative to that of the NPN transistor to avoid emitter-to-collector punch-through.
IBM Technical Disclosure Bulletin entitled "Complementary Bipolar Transistor Process Using Seven Masking steps" by Abbas et al, Vol. 16, No. 5, Pages 1630-1631, October 1973 describes a complementary vertical PNP transistor fabrication. The NPN has an epi-base and the collector definition is accomplished by differential outdiffusion. As a result, the problems of base width control and low emitter-collector punch-through voltage are inevitable.
IBM Technical Disclosure Bulletin entitled "Nine-Mask Complementary Bipolar Process" by Doo, Vol. 22. No. 5, pages 1874-1878, October 1979 describes a complementary vertical NPN and PNP fabrication process. The PNP transistor is composed of an up-diffusion subcollector, N-epi base and polysilicon contacts. Performance of the NPN is deliberately degraded by increasing the collector-substrate junction capacitance in order to improve the PNP device properties.
IBM Technical Disclosure Bulletin entitled "Complementary Bipolar Device Structure" by Chang et al, Vol. 17, No. 1, pages 21-22, June 1974 describes a complementary vertical transistor fabrication process. The PNP transistor resulting from this process includesm an N- substrate with up-diffused P+ subcollector, an N epi base. The PNP emitter doping is not self-aligned to the PNP emitter contact.
Thus, the prior art efforts to obtain a complementary bipolar structure with matched NPN and PNP performance characteristics invariably involve degrading the performance of the NPN to match the performance of the PNP. Another problem with the prior art methods of fabricating complementary bipolar devices is that they invariably involve additional thermal cycles over and above those required for fabrication of the NPN structure alone. These thermal cycles lead to a disruption of the NPN device fabrication making it impossible to obtain good NPN and PNP devices on the same structure. Yet another problem is that since the PNP collector is invariably formed by doping prior to the epitaxial layer deposition, this leads to lack of control of the PNP base width dimension and tolerance due to upward diffusion of the P dopant from the collector into the epitaxial layer during the growth of the epitaxial layer. This is further aggravated by the lack of precise controllability of the epitaxial layer thickness. The net result is a PNP device of significantly inferior performance than that of the NPN device.
It would be desirable to provide a complementary bipolar device pair on a common semiconductor substrate having matched high performance characteristics. It would also be desirable to provide a controllable and reliable process for forming such a complementary structure.